This invention relates to a gate pulse phase shifter or, more particularly, to a gate pulse phase shifter for controlling the phase of a gate pulse impressed on an AC-DC converter constituted, for example, of a thyristor.
FIG. 1 is a block diagram representing a conventional gate pulse phase shifter. In FIG. 1, a synchronizing power input terminal 1 is supplied with a synchronizing AC supply voltage V.sub.AC. A voltage detector 2 detects a voltage of the synchronizing supply voltage V.sub.AC. A phase difference detector 3 compares the phase of the output of the voltage detector 2 with the phase of an output of a ring counter 4 and generates an output according to the phase difference. A voltage control oscillator 5 zeroes the difference between the phase of the output of the voltage detector 2 and that of the output of the ring counter 4 by changing an oscillation frequency according to the output of the phase difference detector 3. A frequency divider 6 divides the oscillation frequency of the voltage control oscillator 5 to impress the same on the ring counter 4. The ring counter 4 counts the output pulse number impressed thereon by the frequency divider 6 and generates six outputs U-Y each shifted 60 degrees in phase from the others, and thus a phase synchronous circuit 7 is formed by the phase difference detector 3, ring counter 4, voltage control oscillator 5 and frequency divider 6.
Pulse generators (8U)-(8Y) generate gate pulses for six thyristors (not illustrated) consituting an AC-DC converter (not illustrated) via output terminals (9U)-(9Y), with the oscillation frequency of the voltage control oscillator 5 as clock pulses and the output signals U-Y of the ring counter 4 as reset pulses, respectively, for binary counters (801U)-(8014). The counters are phase angle specifying devices counting the oscillation frequency of the voltage control oscillator 5 as a clock pulse and resetting a discrete value to 0 with the output signals U-Y of the ring counter 4 as reset pulses. Digital-analog converters (hereinafter referred to as "D-A converters") (802U)-(802Y) convert a digital value, i.e. a discrete value of the binary counters (801U)-(801Y) into an analog value, and comparators (803U)-(803Y) compare this value with a phase reference signal E.sub.C input via a phase signal input terminal (10). The comparators generate an output when both these values coincide with each other.
The operation of the above device will now be described with reference to FIG. 2. The phase synchronous circuit 7 synchronizes the phase of an output of the ring counter 4 with the phase of the synchronizing supply voltage V.sub.AC input via the synchronizing supply input terminal 1. When there is a differenc between the phase of the output of the voltage detector 2 and the phase of the output of the ring counter 4, the phase difference detector 3 generates an output corresponding to the phase difference to change the oscillation frequency of the voltage control oscillator 5, thereby zeroing said phase difference.
In this case, if the frequency of the synchronizing supply voltage V.sub.AC is represented by f, the frequency dividing ratio of the frequency divider 6 is R, and the frequency dividing ratio of the ring counter 4 is 6, the oscillation frequency f.sub.osc of the voltage control oscillator 5 is given by f.sub.osc =6.times.R.times.7. The six output signals U-Y of the ring counter 4 have a phase difference of 60 degrees each, as shown in U-Y of FIG. 2 at (4),and the rise time of each output signal U-Y indicates the gate pulse phase in the case where a control angle of lag .alpha. output to the six thyristors (not illustrated) is 0 degrees. As indicated by the dotted line in FIG. 2 at (4), the output signal U is synchronized in frequency and phase with the synchronizing supply voltage V.sub.AC, and repeats the outputs 0, 1 every 180 degrees.
Discrete values of the binary counters (801U)-(801Y) are reset at the rise time of the output signals U-Y. The binary counters (801U)-(801Y) are of n bits and have n, and R set to satisfy 2.sup.n .gtoreq.6R. Namely, the reset pulses representing the output signal U-Y of the ring counter 4 output at each cycle of the synchronizing supply voltage V.sub.AC come in before the binary counters (801U)-(801Y) count from 000 . . . 0 up to 111 . . . 1, and the binary counters (801U)-(801Y) are then reset to 000 . . . 0 to commence counting anew.
The discrete values of the counters are converted into analog values by the D-A converters (802U)-(802Y), and the outputs of the D-A converters are synchronized, as shown in U-Y of FIG. 2 at (802), with the synchronizing supply voltage V.sub.AC, and are turned into sawtooth waves having a phase difference of 60 degrees each. These sawtooth waves, which are the outputs of the D-A converters (802U)-(802Y), rise at the time of the control angle of lag .alpha.=0 to the six thyristors (not illustrated), increases until the time .alpha.=360 degrees and then return to 0. The sawtooth waves are compared with the phase reference signal E.sub.C input via the phase signal input terminal 10 by the comparators (803U)-(803Y), and when both coincide, as shown in FIG. 2 at (802), output pulses are generated at the output terminals (9U)-(9Y) as shown in (9U)-(9Y) of FIG. 2. These output pulses are generated at the control angle of lag .alpha.=0 when the phase reference signal E.sub.C is 0, and the lag .alpha. increases in accordance as the phase reference signal level E.sub.C becomes larger.
Thus in the conventional device, since the output pulses are generated at the output terminals (9U)-(9Y), the phase of the synchronizing supply voltage V.sub.AC is not used directly, but the phase of the voltage control oscillator 5 produced by the phase synchronous circuit 7 and synchronized with the synchronizing supply voltage V.sub.AC is used. Therefore the output pulses are generated at output terminals (9U)-(9Y) at intervals of 60 degrees at all times, without being influenced by distortions in the synchronizing supply voltage V.sub.AC.
In the conventional device, however, the phase reference signal E.sub.C and the control angle of lag .alpha. are proportionally related to one another. On the other hand, the DC output voltage of the AC-DC converters (not illustrated) using output pulses of the output terminals (9U)-(9Y) as gate pulses is, as well known, proportional to cos .alpha.. Therefore, insofar as the output pulses at the output terminals (9U)-(9Y) generated by the conventional device are used as gate pulses for the AC-DC converters (not illustrated), the phase reference signal E.sub.C is not proportional to the DC output voltage of the AC-DC converters.
As a result, in the case where the DC output voltage of the AD-DC converters is used for control, or where the DC output current is subjected to feedback control, the control system becomes nonlinear and lacks good control response, and moreover, the selection of the control constant becomes complicated.